A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS

📋 论文概要

该论文实现了一款1.2V供电、4.5mW功耗的10位100MS/s流水线ADC，采用65nm CMOS工艺，适用于WiFi/WiMAX等宽带无线应用，解决了低电压下高精度低功耗转换的难题。

💡 主要创新点

• 在65nm CMOS工艺中采用1.2V低电压设计，实现了100MS/s采样率和10位分辨率，功耗仅4.5mW
• 通过优化流水线级架构和低功耗电路技术（如动态比较器、低摆幅放大器），在保持精度的同时显著降低功耗

🏷 关键词

📄 原文摘要

Applications using broadband digital wireless modulation require high-resolution low-power ADC over a bandwidth of few megahertz. For a WiFi or a WiMAX standard, an ADC of ~10b resolution in 5 to 20MHz bandwidth is needed. Its sampling frequency should be in a ratio of 5× the channel bandwidth to simplify the anti-aliasing filter. In order to integrate the ADC with the digital functions in an advanced CMOS technology, compliance with the thin-oxyde voltage supply is necessary. A low-power 1.2V pipelined ADC is implemented in a 65nm CMOS process to achieve 10b resolution at 100MS/s based on the use of a dedicated thin-oxyde high-performance analog (HPA) MOS transistor. The pipeline ADC, shown in Fig. 12.7.1(a), is composed of eight 1.5b pipelined stages followed by a 2b flash converter as the last stage. In order to optimize the power consumption, the capacitances and the bias current of each stage have been scaled down

👥 作者与机构

Mounir Boulemnakher, Eric Andre, Jocelyn Roux, Frederic Paillardet

STMicroelectronics, Crolles, France