A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

📋 论文概要

该论文提出了一种用于GSM/GPRS/EDGE系统的全数字锁相环（ADPLL），通过环路增益校准和相位噪声消除技术实现无分数杂散，同时利用RC滤波器线性化硬开关信号以降低电源/衬底噪声耦合，满足发射输出频谱的严格杂散和相位噪声要求。

💡 主要创新点

• 提出数字环路增益校准技术，精确控制数字前馈路径中的增益值。
• 采用相位噪声消除方法，抑制相位噪声对发射频谱的影响。
• 通过RC滤波器线性化硬开关信号，减少电源/衬底噪声耦合，改善杂散性能。

🏷 关键词

📄 原文摘要

therefore the amount of power/substrate-noise coupling to DCO core is greatly reduced, improving spur performance. To further suppress switching noise, the simple RC filter can be turned on to linearize a hard-switching signal. The digital loop gain calibration for the ADPLL is explained in Fig. 10.1.4. The value of the gain controller in the digital feed-forward path can be precisely calibrated and expressed as MediaTek, HsinChu, Taiwan A key specification for GSM/GPRS/EDGE systems is the transmitter output spectrum 400kHz away from the carrier, which imposes stringent spur and phase-noise requirement for the synthesizer. Most synthesizers for mobile applications are fractionalN-based PLLs. However, the associated fractional spurs must be suppressed, which requires large RC filters and precise loop-gain control when traditional analog techniques are applied. Rapid scaling of CMOS technology enables all-digital PLLs (ADPLLs)

👥 作者与机构

Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh