A 24GS/s 6b ADC in 90nm CMOS

📋 论文概要

本文提出了一款采用90nm CMOS工艺实现的24GS/s、6位分辨率模数转换器（ADC），用于支持10-40Gb/s光通信系统中的DSP均衡。该ADC在保持低功耗的同时实现了高速采样，解决了现有InP和BiCMOS工艺中分辨率与速度的折衷问题。

💡 主要创新点

• 采用时间交织（time-interleaved）架构，通过16个子ADC并行工作实现24GS/s的采样率。
• 在90nm CMOS工艺中实现了6位精度，同时保持低功耗和较小的芯片面积。
• 设计了高速比较器与低失配前端电路，以在Nyquist频率下维持高有效位数（ENOB）。

🏷 关键词

📄 原文摘要

Robert Gibbins1, Yuriy Greshishchev1, Naim Ben-Hamida1, Daniel Pollex1, John Sitch1, Shing-Chi Wang1, John Wolczanski1 1 Nortel, Ottawa, Canada STMicroelectronics, Crolles, France 2 New receivers for 10-to-40Gb/s optical communications rely on DSP-based equalization to correct for fiber impairments and enhance channel spectral efficiency [1-3]. This requires a 6b ADC with sampling rate that is twice the data rate and low ENOB degradation up to the Nyquist frequency. Previously a 24GS/s ADC was designed in InP technology [3] with only 3b resolution and a 5b 22GS/s BiCMOS ADC reported in our earlier work [4] required 3W and was not suitable for integration with DSP core in an advanced CMOS technology. A 20GS/s 8b ADC implemented in 0.18µm CMOS [5] achieved 4.6b at 6GHz input, but consumed 9W. Lower sampling rate converters include a 10GS/s 5b ADC in SiGe BiCMOS [2] and a 12.5GS/s 4.5b ADC in 65nm CMOS [6]. This

👥 作者与机构

Peter Schvan1, Jerome Bach2, Chris Falt1, Philip Flemke1,