A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC

📋 论文概要

提出一种14位100MS/s流水线ADC，通过合并有源采样保持器（S/H）与第一级MDAC来消除显式有源S/H，从而降低功耗。解决了传统无S/H架构在高速下需增加功耗的缺点，实现了低功耗高速转换。

💡 主要创新点

• 合并有源S/H和第一MDAC，消除独立有源S/H，减少功耗。
• 通过优化时序和电路结构，克服无S/H架构在高速下的限制，保持高分辨率。

🏷 关键词

📄 原文摘要

University of Texas, Austin, TX, 2National Semiconductor, Salem, NH Low-power consumption is a key specification in many electronic systems, such as wireless communication and imaging systems. One of the most efficient ways to achieve low-power operation is opamp-sharing between successive pipeline stages [1]. Recently, further power saving has been achieved by removing the explicit active S/H. While the ADC without a S/H successfully reduces power consumption, it has two drawbacks. First, it cannot operate at high speed without increasing power, because it requires a short comparison phase between the sampling and amplification phases of the first stage [2, 3] and an additional feedback capacitor decreases the feedback factor [2]. This issue can be relaxed by dividing the sampling phase into two, using the second half of the divided phase for comparison [4]. However, this division is not suitable for a high-speed high-resolution ADC, which demands highlinearity input sampling and a

👥 作者与机构

Byung-Geun Lee1, Byung-Moo Min2, Gabriele Manganaro2, Jonathan W. Valvano1