A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

📋 论文概要

本文提出一种模块化全数字PLL架构，在65nm CMOS工艺中实现了两个PLL：一个覆盖1-2GHz，另一个覆盖24-32GHz。解决了传统模拟PLL在可移植性、可编程性和噪声抑制方面的不足，通过模块化设计实现了构建块的共享。

💡 主要创新点

• 提出了一种模块化全数字PLL架构，允许在不同性能目标的设计点之间共享构建块。
• 在标准65nm CMOS工艺中同时实现了1-2GHz和24-32GHz两个宽频段操作，展示了全数字PLL的宽调谐范围能力。

🏷 关键词

📄 原文摘要

H. A. Ainspan1, D. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY Texas A&M University, College Station, TX 2 Digital phase-lock loop (DPLL) design approaches offer multiple advantages, including compactness, broad programmability and testability, noise immunity, direct migration between technology nodes, and enhanced robustness to process variation [1-4]. In addition, DPLLs can be made modular, enabling the sharing of building blocks between design points targeting different performance goals or feature sets. We report two DPLLs fabricated in a standard 65nm bulk CMOS process. One PLL, targeting 1-to-2GHz clock generation for the ASIC consumer market, is realized using a 5-stage static–CMOS-ring digitally-controlled oscillator (ringDCO). The second PLL, an exploratory design for 20-to-30GHz applications, is realized using an LC-tank DCO. Both PLLs use the same proportional-integral (PI) loop filter, ΔΣ modulator (ΔΣM),

👥 作者与机构

A. V. Rylyakov1, J. A. Tierno1, D. Z. Turker2, J.-O. Plouchart1,