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本文提出了一种在90纳米数字CMOS工艺下实现的24平方毫米四频单芯片GSM无线电收发器,集成了RF收发器和数字基带处理器,并通过发射机校准解决了模拟电路在先进数字CMOS中的性能退化问题。
I. Bashir, C.-M. Hung, J. Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, J. Mehta, S. Glock, T. Almholt, S. Bhatara Texas Instruments, Dallas, TX The recent demand for ultra-low-cost cell phones by billions of firsttime users in the developing countries has spurred development of single-chip 2G radios that integrate an RF transceiver with a digital baseband (DBB) processor in scaled CMOS, for example, GSM in 0.13µm [1] and PHS in 0.18µm [2]. The ultimate goal of a phoneon-a-chip has not yet been realized due to various integration issues of low-voltage CMOS with 2W RF power amplifiers (PAs), 20V battery chargers, and RX SAW filters. Hence, the integration at the RF and DBB level still provides the lowest-cost solution.
R. B. Staszewski, D. Leipold, O. Eliezer, M. Entezari, K. Muhammad,