A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

📋 论文概要

本文提出一种采用90nm CMOS工艺实现的39.1-41.6GHz ΔΣ小数-N频率合成器，工作电压1.2V，功耗64mW。通过使用注入锁定分频器（ILFD）并引入数字校准技术，解决了ILFD锁定范围有限的问题，实现了低功耗毫米波频率合成。

💡 主要创新点

• 采用注入锁定分频器（ILFD）作为反馈环路的第一级分频器，在毫米波频段实现低功耗分频。
• 提出数字校准技术克服ILFD的锁定范围限制，无需额外模拟调谐，提高锁相环的鲁棒性。
• 整体合成器覆盖39.1-41.6GHz频率范围，功耗仅64mW，适合多Gb/s消费类毫米波应用。

🏷 关键词

📄 原文摘要

making mmwave technology attractive for multi-Gb/s consumer-market applications. A key building block of the mm-wave transceiver is the frequency synthesizer. In this paper, we present a 39.1-to-41.6GHz 1.2V 64mW ΔΣ fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divideby-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations. One of the most critical blocks in the PLL is the first stage of the frequency divider. Due to speed requirements, an injection-locking divider-by-2 is typically used. To cover the required VCO frequency range and process-voltage-temperature (PVT) variations, the

👥 作者与机构

Stefano Pellerano1, Rajarshi Mukhopadhyay2, Ashoke Ravi1,

Joy Laskar3, Yorgos Palaskas1 1 Intel, Hillsboro OR, 2Texas Instruments, Dallas, TX Georgia Institute of Technology, Atlanta, GA 3 The unlicensed bandwidth available at 60GHz is