A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

📋 论文概要

该论文提出了一种在bulk CMOS工艺中实现的500MHz随机存取嵌入式1Mb DRAM宏单元，解决了传统嵌入式DRAM速度较慢的问题，满足了90nm及以下工艺节点SoC集成的高密度、低软错误率需求。

💡 主要创新点

• 实现了500MHz随机存取速度的嵌入式DRAM宏单元，显著提升了传统eDRAM的操作频率。
• 可能采用了优化的列访问架构或电路技术，在不显著增加面积的前提下提高了读写速度。
• 在bulk CMOS工艺中实现了与SRAM兼容的随机存取接口，降低了SoC集成复杂度。

📄 原文摘要

Cormac O’Connelll, Sreedhar Natarajan1, Chris Huang2, Chuan-Yu Wu2, Min-Jer Wang2, C. J. Wang2, Paul Chen2, Rick Hsieh2 1 TSMC Design Technology Canada, Kanata, Canada TSMC, Hsinchu, Taiwan 2 From 90nm and below, SoC integration is reaching the point where it makes technical and economic sense to integrate embedded DRAM (eDRAM) onto a die. While eDRAMs have 2.5× to 4× density compared to SRAMs and have lower soft-error rate they are slower in operation due to inherent architecture [1]. In a conventional DRAM with a single column access device for read and write, a write operation is started only after the bitline sense amplifiers are turned on and the bitlines are well on their way to full restoration. This is to avoid destroying data due to premature access to global bitlines in the non-writing columns. This delay in the write operation increases row cycle time to allow the storage node to be fully written. Accelerating write cycle with early access

👥 作者与机构

Sergey Romanovsky1, Atul Katoch1, Arun Achyuthan1,