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ISSCC 2008Session 28 · NON-VOLATILVE MEMORY & DIGITAL CLOCKINGDigital Circuits

An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU m2, WSM judges it as the degradation of erase time and sets the erase time degradation detect bit in the status register.

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📋 论文概要

该论文提出了一种用于汽车MCU的8kB EEPROM仿真DataFLASH模块,通过结合擦除时间退化检测位和背景操作的软件均衡方案,显著提高了P/E耐久性。解决了EEPROM仿真中耐久性受限的问题。

💡 主要创新点

重要性
发表年份
ISSCC 2008

🏷 关键词

EEPROM仿真DataFLASH汽车MCU耐久性软件均衡背景操作

📄 原文摘要

Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi Figure 28.2.5 shows a software-leveling scheme with background operation (BGO) between a 512kB code Flash (with 50MHz highspeed page read mode) and 8kB E2FLASH that further improves P/E endurance. The improvement uses the combination of the erase-time degradation-detect bit and BGO. The software-leveling scheme is also available for an increase in the allowed maximum value of P/E cycle in a limited block when a low failure rate of P/E endurance is desired. This software-leveling scheme is performed in following steps. First, the 512kB code Flash stores an address mapping, which is used to swap the erase block that has reached 1M P/E cycles. Then the CPU monitors the erase-time degradation-detect flag. If CPU detects the flag, CPU reads out the address mapping from the code Flash by using BGO and swaps a degraded erase block to some fresh blocks in the 8kB E2FLASH. When

👥 作者与机构

Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe,

分类:Digital Circuits · 年份:ISSCC 2008