⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一种能量高效且抗亚稳态的时序错误检测与基于指令重放的恢复电路，在65nm CMOS测试芯片中实现，旨在消除因电源电压和温度波动导致的时钟频率设计余量，从而提升处理器能效。
Chris B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De Intel, Hillsboro, OR Microprocessor clock frequency (FCLK) is traditionally determined based on maximum supply voltage (Vcc) droop and temperature specifications. Since typical usage patterns usually run at nominal Vcc and temperature, these infrequent dynamic variations severely limit FCLK. The concept of timing-error detection and correction in previous work [1,2] is extended and implemented in a test-chip in 65nm CMOS [3] to explore the effectiveness of resilient circuits in eliminating Vcc and temperature FCLK guardbands as well as exploiting path-activation probabilities to maximize throughput (TP). Three error-detection sequential circuits (Fig. 22.2.1) are implemented. The first technique is a simplified Razor flip-flop (RFF) [1,2] with the metastability detector omitted. The RFF double samples input data with a datapath flip-flop and a shadow latch. The flip-flop
Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee,