A 20Gb/s 40mW Equalizer in 90nm CMOS Technology

📋 论文概要

本文提出了一种在90nm CMOS工艺下实现的20Gb/s、40mW均衡器，旨在解决高速串行链路中FR4印制电路板带来的信号损耗问题。该均衡器通过低功耗设计实现了高数据率的均衡，降低了芯片引脚数和PCB布线复杂度。

💡 主要创新点

• 采用一种低功耗的均衡器架构，在20Gb/s数据率下仅消耗40mW功率。
• 针对FR4背板信道的高频损耗，实现了有效的信号恢复和眼图张开。

🏷 关键词

📄 原文摘要

In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it lowers the number of output drivers while maintaining the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In

👥 作者与机构

Sameh A Ibrahim, Behzad Razavi

University of California, Los Angeles, CA