ISSCC 2010
Session 1
Plenary
MEMS for Automotive and Consumer Electronics Jiri Marek
A car is skidding, and stabilizes itself without driver intervention; a laptop falls to the floor, and protects the hard drive by parking the read/write drive head automatically before impact; an airbag fires before the
ISSCC 2010
Session 1
Plenary
Harnessing Technology to Advance the Next-Generation Mobile User-Experience This paper will examine the status of each challenge, and ascertain where we need to be in the future, in order to deliver a compelling user experience within the constraints of a smart mobile-companion device. Greg Delagi 2. The Smart-Mobile-Companion Device of the Future
The mobile-handset market continues to be a dynamic and growing one, enabled by technology advances that include increased bandwidth, greater processing performance, increased power efficiency, and improved display techn
ISSCC 2010
Session 1
Plenary
Challenges of Image-Sensor Development Tomoyuki Suzuki
Due to steady advancements in semiconductor technology, greatly-enhanced memory capacity and high-speed data processing are now available, creating many evolving types of audio and video electronic products. The digital
ISSCC 2010
Session 1
Plenary
New multi-gate transistor structures such as the FinFET and Trigate FET provide opportunities to reduce channel lengths that are controlled largely by the thin body of the fin instead of by channel doping [8,9]. Reduced susceptibility to random channel-doping fluctuations, improved drain-induced-barrier lowering, smaller sub-threshold swing, and improved channel carrier mobility due to smaller vertical electric fields, are advantages offered by the FinFET and
The materials and device-structure innovations discussed in the three preceding paragraphs, although not explicitly considered in the original scaling theory of MOSFETs, provide significant opportunities to continue to s
ISSCC 2010
Session 10
Power Management
A Two-phase Switching Hybrid Supply Modulator for Polar Transmitters with 9% Efficiency Improvement
Emerging polar transmitters for highly efficient and linear power amplifiers (PAs) demand for high-efficiency, high-bandwidth and low-ripple supply modulators. In [1], a linear regulator is used; however, its efficiency
ISSCC 2010
Session 10
Power Management
A Robust Digital DC-DC Converter with Rail-to-Rail Output Range in 40nm CMOS
TSMC, Austin, TX The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processe
ISSCC 2010
Session 10
Power Management
A PLL-Based High-Stability Single-Inductor 6-channel Output DC-DC Buck Converter
particular for portable systems where typically multiple voltage levels are required to achieve multi functionality. To meet these requirements, a singleinductor multiple-output (SIMO) switching converter is a very stron
ISSCC 2010
Session 10
Power Management
A 300mA 14mV-Ripple Digitally Controlled Buck Converter Using Frequency Domain ΔΣ ADC and Hybrid PWM Generator 6415 = ORJ
Digitally controlled DC-DC converters enable design portability as well as reconfigurable compensation and control schemes. Digital controllers are also resistant to process and temperature variations making them attract
ISSCC 2010
Session 10
Power Management
A 10MHz 92.1%-Efficiency Green-Mode Automatic Reconfigurable Switching Converter with Adaptively Compensated Single-Bound Hysteresis Control
Nowadays switching DC-DC converters have become indispensable in powerefficient VLSI systems. As operation frequency increases, load fluctuations in such a device require high switching frequencies in DC-DC converters fo
ISSCC 2010
Session 10
Power Management
Digitally Assisted Discontinuous Conduction Mode 5V/100MHz and 10V/45MHz DC-DC Boost Converters with Integrated Schottky Diodes in Standard 0.13µm CMOS
in a low-voltage process can be attractive for smaller and lighter portable devices powered from single-cell batteries (i.e., NiMH, Fuel cells). To reduce the size of the off-chip components both high frequency (10 to 10
ISSCC 2010
Session 10
Power Management
A 0.16mm2 Completely On-Chip Switched-Capacitor DC-DC Converter Using Digital Capacitance Modulation for LDO Replacement in 45nm CMOS
Massachusetts Institute of Technology, Cambridge, MA Iowa State University, Ames, IA 3 Texas Instruments, Dallas, TX 2 Reducing power consumption through VDD scaling is a major trend in nanometer CMOS circuits. In modern
ISSCC 2010
Session 10
Power Management
A 32nm Fully Integrated Reconfigurable SwitchedCapacitor DC-DC Converter Delivering 0.55W/mm2 at 81% Efficiency
and drain voltages can reside anywhere among Vi, (Vi/2+Vo/2), Vo, and (Vo/2) in the 3 modes of operation. Fortunately however, the physical/logical ordering of the standard cells can be leveraged to realize a simplified
ISSCC 2010
Session 11
mm-Wave
A 4-Channel 4-Beam 24-to-26GHz Spatio-Temporal RAKE Radar Transceiver in 90nm CMOS for Vehicular Radar Applications
is a future environment that is adaptive and responsive to the objects and human beings that occupy it. Wideband RF and mm-Wave radar and imaging sensors will play a key role for indoor and outdoor surveillance, search a
ISSCC 2010
Session 11
mm-Wave
A Fully Integrated 77GHz FMCW Radar System in 65nm CMOS
Millimeter-wave anti-collision radars have been widely investigated in advanced CMOS technologies recently. This paper presents a fully integrated 77GHz FMCW radar system in 65nm CMOS. The FMCW radar transmits a continuo
ISSCC 2010
Session 11
mm-Wave
A SiGe BiCMOS 16-Element Phased-Array Transmitter for 60GHz Communications gy. A stand-alone single-element breakout has a measured 60GHz OP1dB that can vary from +3dBm to +15dBm with a nearly constant peak PAE of 9%.
Ping-Yu Chen3, Scott Reynolds1, Jing-Hong Conan Zhan3, Brian Floyd1 The Tx has been fully characterized on-wafer. The output power from an individual element is measured, for CW input, for different phase (and correspond
ISSCC 2010
Session 11
mm-Wave
A Wideband mm-Wave CMOS Receiver for Gb/s Communications Employing Interstage Coupled Resonators
Superiori di Pavia, Pavia, Italy 3 STMicroelectronics, Pavia, Italy 4 STMicroelectronics, now with Broadcom, Bunnik, Netherlands 5 University of Modena e Reggio Emilia, Modena, Italy 2 Multi-Gb/s wireless communications,
ISSCC 2010
Session 11
mm-Wave
A 2.4GHz/915MHz 51µW Wake-Up Receiver with Offset and Noise Suppression
sensor networks (WSN), an always-on wake-up receiver (WuRx) can be used to monitor the radio link continuously. For truly autonomous sensor nodes employing energy scavenging, only 50µW power is available for the WuRx [1]
ISSCC 2010
Session 11
mm-Wave
A 2.4GHz 830pJ/bit Duty-Cycled Wake-Up Receiver with -82dBm Sensitivity for Crystal-Less Wireless Sensor Nodes
Lucien J. Breems1, Kofi A. A. Makinwa3, Bram Nauta2 1 NXP Semiconductors, Eindhoven, Netherlands University of Twente, Enschede, Netherlands 3 Delft University of Technology, Delft, Netherlands 2 This paper describes a 2
ISSCC 2010
Session 11
mm-Wave
An Ultra-Low-Power Interference-Robust IR-UWB Transceiver Chipset Using Self-Synchronizing OOK Modulation
Columbia University, New York, NY Politecnico di Torino, Torino, Italy 3 Peking University, Beijing, China 4 Instituto Superior Tecnico, Lisbon, Portugal 2 Impulse Radio-UWB (IR-UWB) is actively being researched as a low
ISSCC 2010
Session 11
mm-Wave
A Fully Integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with Digital RRC Synthesis
15.4a low-rate WPAN standard adopts Impulse-Radio UWB (IR-UWB) to provide a low-power communication system with improved communication range, robustness, and mobility. Furthermore its standardized low-cost and high-accur
ISSCC 2010
Session 11
mm-Wave
A 0.92/5.3nJ/b UWB Impulse Radio SoC for Communication and Localization
X. Liu1, Y-S. Wang1, X-J. Yuan1, C. H. Heng2 1 Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore 2 National University of Singapore, Singapore UWB has shown great potential fo
ISSCC 2010
Session 12
Medical & Bio
Pain Control On Demand Based on Pulsed RadioFrequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC
I-Hsiu Ho2, Po Hsiang Fang1, Yi Chin Li1, Chang Lun Wang1, Yao-Chuan Tsai1, Yeong-Ray Wen3, Win-Pin Shih1, Yao-Joe Yang1, Shey-Shi Lu1 1 National Taiwan University, Taipei, Taiwan National Taipei University of Technology
ISSCC 2010
Session 12
Medical & Bio
Mixed-Signal Integrated Circuits for Self-Contained Sub-Cubic Millimeter Biomedical Implants
Purdue University, West Lafayette, IN Texas Instruments, Dallas, TX 2 Development of fully wireless miniature implantable medical devices is challenging due to inefficiencies of electrically small antennas and tissue-ind
ISSCC 2010
Session 12
Medical & Bio
An Implantable 5mW/Channel Dual-Wavelength Optogenetic Stimulator for Therapeutic Neuromodulation Research
technology of many neurological therapies, electrical stimulation suffers from several drawbacks. Constraints on electrode geometry and placement can result in an inability to modulate specific neural populations, and st
ISSCC 2010
Session 12
Medical & Bio
Compact Voltage and Current Stimulation Buffer for High-Density Microelectrode Arrays
ETH Zürich, Zürich, Switzerland ETH Zürich (now at IBM Research), Zürich, Switzerland 3 University of Tokyo, Tokyo, Japan 2 The most sophisticated information processing system, the human brain, consists of a huge number
ISSCC 2010
Session 13
Clocking & PLLs
A Low-Area Switched-Resistor Loop-Filter Technique for Fractional-N Synthesizers Applied to a MEMSBased Programmable Oscillator
Shouvik Mukherjee1, Cathy Lee1, Vadim Tsinker4, Sathi Perumal5, Benjamin Soto6, Niveditha Arumugam1, Bruno W Garlepp1 1 SiTime, Sunnyvale, CA University of California, Los Angeles, CA 3 Global Foundries, Sunnyvale, CA 4
ISSCC 2010
Session 13
Clocking & PLLs
A 45nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O
Oshima1, Bruce Andrew Doyle1, Roland Bakalski2, Richard Joseph DeSantis1, Anand Thiruvengadam1, Charles Lin Wang1, Gerry Robert Talbot1, Emerson S Fang1 1 AMD, Sunnyvale, CA Global Foundries, Dresden, Germany 2 As proces
ISSCC 2010
Session 13
Clocking & PLLs
A 0.3mm2 90-to-770MHz Fractional-N Synthesizer for a Digital TV Tuner
Fujitsu Laboratories, Yokohama, Japan Fujitsu Laboratories, Kawasaki, Japan 2 This paper describes a 0.3mm2 and a 90M-to-770MHz range low spurious fractional-N synthesizer, with which mobile receivers for Japanese terres
ISSCC 2010
Session 13
Clocking & PLLs
A Low-Noise Frequency Synthesizer for Infrastructure Applications
David Stegmeir, Li Jin RFMD, San Jose, CA Because of higher performance requirements, infrastructure transceivers have historically employed lower levels of on-chip integration than their handset counterparts. One of the
ISSCC 2010
Session 13
Clocking & PLLs
A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for Wireless HD Applications
Cedric Dufis1, Pierre Busson1, Pierre Vincent2, Didier Belot1, Pascal Urard1 1 STMicroelectronics, Crolles, France CEA-LETI-Minatec, Grenoble, France 3 STMicroelectronics, Grenoble, France 2 This work shows a complete PL
ISSCC 2010
Session 14
Memory
Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13µm CMOS
random-access memory (MRAM) [1-3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, t
ISSCC 2010
Session 14
Memory
A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes
Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe The voltage generators for t
ISSCC 2010
Session 14
Memory
A 0.13µm 64Mb Multi-Layered Conductive MetalOxide Memory
Sri Rama Namala, Misako Matsuoka, Bruce L Bateman, Darrell Rinerson Unity Semiconductor, Sunnyvale, CA A number of technologies have been proposed to replace NAND Flash as scaling becomes more difficult [1-2]. One promis
ISSCC 2010
Session 14
Memory
A Scalable Shield-Bitline-Overdrive Technique for 1.3V Chain FeRAM
Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Sumiko Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Ta
ISSCC 2010
Session 14
Memory
A 2.5Gb/s/ch 4PAM Inductive-Coupling Transceiver for Non-Contact Memory Card
An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact
ISSCC 2010
Session 14
Memory
A 0.29V Embedded NAND-ROM in 90nm CMOS for Ultra-Low-Voltage Applications
Hsinchu, Taiwan 3 Fukuoka Institute of Technology, Fukuoka, Japan 2 Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-VDDmin-delay-product embedded ROM for storing fixed p
ISSCC 2010
Session 14
Memory
A 90nm 4Mb Embedded Phase-Change Memory with 1.2V 12ns Read Access Time and 1MB/s Write Throughput
Marco Pasotti1, Massimo Borghi1, Paolo Mattavelli1, Paola Zuliani1, Luca Scotti1, Gianfranco Mastracchio1, Ferdinando Bedeschi2, Roberto Gastaldi2, Roberto Bez2 1 STMicroelectronics, Agrate Brianza, Italy Numonyx, Agrate
ISSCC 2010
Session 14
Memory
A 45nm 1Gb 1.8V Phase-Change Memory
voltage depending on the device configuration. In the voltage-forcing approach, a cell-position-compensation system is implemented to reduce the parasitic effect. The WL compensation is based on adding a resistive path t
ISSCC 2010
Session 15
Digital Processors
A 390Mb/s 3.57mm2 3GPP-LTE Turbo Decoder ASIC in 0.13µm CMOS
devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years
ISSCC 2010
Session 15
Digital Processors
A 4.5mW Digital Baseband Receiver for Level-A Evolved EDGE
given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry’s only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially d
ISSCC 2010
Session 15
Digital Processors
A 477mW NoC-Based Digital Baseband for MIMO 4G SDR
processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocol (e.g. 63 for 3GPP-LTE), the numb
ISSCC 2010
Session 15
Digital Processors
A 2Gb/s Network Processor with a 24mW IPsec Offload for Residential Gateways
The Internet has become an important tool to deliver services such as Voice over Internet Protocol (IP) and high-definition video. To enable the widespread use of these services, it is essential to ensure quality-of-serv
ISSCC 2010
Session 15
Digital Processors
A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance
Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De Intel, Hillsboro, OR Microprocessors experience a wide range of dynamic variations, including voltage droo
ISSCC 2010
Session 15
Digital Processors
A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for TransientError Tolerance and Adaptation to PVT Variation
detection and correction of timing errors. A combination of error-detecting circuits and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an effic
ISSCC 2010
Session 15
Digital Processors
A 45nm CMOS 13-Port 64-Word 41b Fully Associative Content-Addressable Register File
The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the techn
ISSCC 2010
Session 15
Digital Processors
Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells
in medical, infrastructure and environmental monitoring. Due to volume constraints, sensor systems are often capable of storing only small amounts of energy. Several systems have increased lifetime through VDD scaling [1
ISSCC 2010
Session 16
Data Converters
A 16b 250MS/s IF-Sampling Pipelined A/D Converter with Background Calibration
Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed Analog Devices, Greensboro, NC Wireless communication applications have driven the de
ISSCC 2010
Session 16
Data Converters
A 16b 100-to-160MS/s SiGe BiCMOS Pipelined ADC with 100dBFS SFDR
The RX signal path in wireless base transceiver stations (BTS) drives the continued development of high-resolution high-speed ADCs. Such ADCs enable BTSs with software-defined and/or multi-carrier capability, such as mul
ISSCC 2010
Session 16
Data Converters
A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS
fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed w
ISSCC 2010
Session 16
Data Converters
A Mostly Digital Variable-Rate Continuous-Time ADC ΔΣ Modulator
modulator is presented that consists mostly of digital circuitry. It does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a lowjitter clock. Unlike conventional ΔΣ
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