GHz DCO with a Frequency Resolution of 150Hz for All-Digital PLL

📋 论文概要

本文提出了一种用于全数字锁相环的GHz级数字控制振荡器，实现了150Hz的极细频率分辨率，有效降低了量化噪声对带外相位噪声的影响，解决了传统DCO频率分辨率不足的问题。

💡 主要创新点

• 采用新型电容阵列结构实现150Hz的超高频率分辨率，优于传统方案。
• 通过优化的数字调谐机制，在保持高分辨率的同时兼顾了振荡器相位噪声性能。

🏷 关键词

📄 原文摘要

In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by

👥 作者与机构

Luca Fanori, Antonio Liscidini, Rinaldo Castello

University of Pavia, Pavia, Italy