A 16b 100-to-160MS/s SiGe BiCMOS Pipelined ADC with 100dBFS SFDR

📋 论文概要

该论文提出了一种16位100-160MS/s的SiGe BiCMOS流水线ADC，用于无线基站接收机。它解决了多载波GSM等应用对高分辨率、高采样率和高线性度ADC的需求，实现了100dBFS的SFDR和大于77dBFS的SNR。

💡 主要创新点

• 采用SiGe BiCMOS工艺实现流水线ADC架构，在100-160MS/s采样率下达到16位精度和100dBFS SFDR，满足严苛的线性度要求。
• 针对无线基站接收机中复杂RF前端简化需求，优化了ADC的动态范围和噪声性能，支持多载波GSM等应用。

🏷 关键词

📄 原文摘要

The RX signal path in wireless base transceiver stations (BTS) drives the continued development of high-resolution high-speed ADCs. Such ADCs enable BTSs with software-defined and/or multi-carrier capability, such as multi-carrier GSM (MC-GSM). ADC requirements have toughened due to the desire to replace complex mixing stages in the RF receiver front-end with the ADC itself. Such receivers combine a high-performance ADC with a simpler RF path to concurrently decode multiple channels. MC-GSM in particular requires an ADC with ~125MS/s sample rate, >77dBFS SNR, and excellent linearity for 100MHz input signals (>100dBc with a -1 dBFS amplitude). The first practical ADC to approach these requirements [1] is implemented in a complementary BiCMOS process. An advantage of this design was the switched current approach that resulted in simple clock schemes and low logic swings that avoided interference with analog signals. However, this design had limited

👥 作者与机构

Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh

Texas Instruments, Dallas, TX