Low-Skew Clock Distribution Using Zero-PhaseClock-Buffer DLLs

📋 论文概要

该论文提出了一种使用零相位时钟缓冲器延迟锁定环（DLL）的低偏斜时钟分布方案，解决了传统H-tree时钟分布网络中因导线和缓冲器不匹配引起的时钟偏斜问题。通过采用DLL替代PLL，实现了多个时钟端点之间的低偏斜同步。

💡 主要创新点

• 提出了零相位时钟缓冲器DLL架构，能够在多个时钟分支之间实现低偏斜，无需复杂的H-tree或网格结构。
• 相比于传统的PLL+H-tree方案，该DLL方法具有更低的相位噪声和更好的匹配特性，简化了时钟分布设计。

🏷 关键词

📄 原文摘要

Carl Werner, Ken Chang Rambus, Los Altos, CA Clock distribution continues to be a challenging task in digital clocked systems. In a typical clocking architecture (Fig. 9.2.1, top), a phase-locked loop (PLL) produces the desired phase/frequency, and an H-tree clock distribution network distributes the generated clock signal to multiple sections (A to D) on the die. Mismatch between the H-tree branches, such as mismatch in wires and clock buffers (B1 to B6), introduce skew between different clock ends CLKA to CLKD. Mesh clocking network may result in skew reduction at the expense of power consumption. To alleviate the power overhead, resonant clocking techniques have been successfully demonstrated in both single-ended [1] and differential

👥 作者与机构

Ting Wu, Farshid Aryanfar, Hae-Chang Lee, Jie Shen, TJ Chin,