A 10b 50MS/s 820µW SAR ADC with On-Chip Digital Calibration

📋 论文概要

提出一种10位50MS/s的SAR ADC，通过片上数字校准技术解决分裂电容DAC的电容失配问题，实现820µW的低功耗。该ADC无需内部时钟发生器，利用数字校准提高精度并简化设计。

💡 主要创新点

• 采用片上数字校准技术，自动校正分裂电容DAC的失配误差，提升转换精度和良率。
• 通过优化SAR逻辑和时钟方案，无需外部高速时钟或内部时钟发生器，降低系统复杂度和功耗。

🏷 关键词

📄 原文摘要

power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity e

👥 作者与机构

Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto

Fujitsu Laboratories, Kawasaki, Japan Rapid growth in the demand for “Green-IT” or medical applications requires