A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) Reconfigurable Transceiver in 45nm CMOS

📋 论文概要

该论文提出了一种在45nm CMOS工艺中实现的5至25Gb/s可重构收发器，通过自适应信令模式（如单端、差分、电流/电压模式）和均衡技术，在1.6至3.8mW/(Gb/s)的功耗效率下，解决了从短距离封装链路到长距离背板等多样化信道的高能效通信问题。

💡 主要创新点

• 提出了一种可重构收发器架构，能够根据信道损耗动态切换信令模式（单端、差分、多电平）和均衡策略，实现宽范围信道下的最优能效。
• 在45nm CMOS工艺中实现了5至25Gb/s的数据速率范围，且功耗效率仅为1.6至3.8mW/(Gb/s)，显著优于传统固定模式收发器。

🏷 关键词

📄 原文摘要

systems span a wide range: from 1-to-2mm on-package links (OPLs) in MCMs, to 25-to-100cm backplanes in server systems. Signaling with optimal power efficiency over such a diverse set of channels requires adaptation of the signaling mode to the channel [1]. For example, single-ended (SE) under-terminated and possibly multilevel signaling may be appropriate for OPL, while differential (DIFFL) source-terminated current/voltage-mode (I/V-mode) signaling with TX and RX equalization might be required for lossier backplane channels. Previous work has demonstrated signaling mode adaptation [2] and power-performance scalability [3] for a narrow range of I/O channels. In this paper, we present a unified transceiver design that can be reconfigured to signal optimally over a wider spectrum of I/O

👥 作者与机构

Ganesh Balamurugan, Frank O’Mahony, Mozhgan Mansuri,

James E Jaussi, Joseph T Kennedy, Bryan Casper Intel, Hillsboro, OR Channels for inter-chip communication in high-speed digital