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本文介绍了IBM POWER7TM处理器的实现，该处理器集成了8个四线程核心、两个内存控制器和高速系统链接，采用45nm CMOS SOI工艺，拥有1.2B晶体管和567mm²的芯片面积。旨在提供高并行性和可扩展性，满足高端服务器的高性能需求。
Joshua Friedrich2, Roland Frech1, James Kahle2, Balaram Sinharoy3, William Starke2, Scott Taylor2, Steve Weitzel2, Sam G. Chu2, Saiful Islam2, Victor Zyuban4 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Poughkeepsie, NY 4 IBM T.J. Watson, Yorktown Heights, NY 2 The next processor of the POWER TM family, called POWER7TM is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm² die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-κ copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm² DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described in [3] and [5].
Dieter Wendel1, Ronald Kalla2, Robert Cargoni2, Joachim Clables2,