A 0.5V 100MHz PD-SOI SRAM with Enhanced Read Stability and Write Margin by Asymmetric MOSFET and Forward Body Bias

📋 论文概要

该论文提出了一种在0.5V电压下工作的100MHz PD-SOI SRAM，通过非对称MOSFET设计和正向体偏置技术，显著提高了读稳定性和写裕量，解决了低电压下SRAM操作裕量不足的问题。

💡 主要创新点

• 采用非对称MOSFET结构，优化了读和写操作时的晶体管特性，增强了读稳定性。
• 利用正向体偏置技术，在低电压下提升写裕量，同时保持低待机漏电流。

🏷 关键词

📄 原文摘要

characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1-3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage. Figure 19.8.1 shows a conventional 6T SRAM composed of pass-gate (PG), pulldown (PD) and pull-up (PU) MOSFETs. The bitcell is designed so that the b ratio (the current ratio IPD/IPG) is larger for the static-noise margin (SNM) while the a ratio (the current ratio of IPU/IPG) is smaller for writability. This is done by optimizing channel length (L) and width (W). The dua

👥 作者与机构

Koji Nii1, Makoto Yabuuchi1, Yasumasa Tsukamoto1, Yuuichi Hirano2,

Toshiaki Iwamatsu2, Yuji Kihara1 1 Renesas Technology, Kodaira, Japan Renesas Technology, Itami, Japan 2 Voltage and technology scaling and increasing random variation in MOSFET