⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文详细介绍了POWER7微处理器中时钟存储元件(CSE)及本地时钟电路的设计，解决了在45nm SOI工艺下高性能微处理器中时钟分配与存储元件的时序、功耗和可靠性问题。
Joshua Friedrich5, Victor Zyuban2, Ethan Cannon6, A.J. KleinOsowski6 1 IBM Systems and Technology Group, Yorktown Heights, NY IBM Research, Yorktown Heights, NY 3 IBM Systems and Technology Group, Boeblingen, Germany 4 IBM Systems and Technology Group, Poughkeepsie, NY 5 IBM Systems and Technology Group, Austin, TX 6 Boeing, Seattle, WA 2 The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7TM chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not only on the area, power, and performance of the chip, but also on the reliability, testability, and the ability to debug and optimize the hardware. This paper will focus on the special features added to the CSE design with these considerations in mind.
James Warnock1, Leon Sigal2, Dieter Wendel3, K Paul Muller4,