A 1.2 TB/s On-Chip Ring Interconnect for 45nm 8-Core Enterprise Xeon® Processor

📋 论文概要

本文介绍了一款用于45nm 8核企业级Xeon处理器的片上环形互连架构，实现了1.2 TB/s的高带宽和低延迟共享L3缓存访问，同时兼顾设计模块化、低功耗和低面积开销。

💡 主要创新点

• 采用环形互连拓扑结构，支持10个环站点（Cbox、Sbox等）的高效通信，满足多核处理器的高带宽需求。
• 通过优化环停布局和信号传输路径，实现了低延迟的共享L3缓存访问，提升了系统性能。
• 设计强调模块化，便于快速推出多款产品，并降低了功耗和硅面积开销。

🏷 关键词

📄 原文摘要

Xeon microprocessors targeting high performance, low-power products [1, 2]. Several key design requirements for this product include high bandwidth, low-latency shared L3 cache access, design modularity to support efficient release of multiple products, and low power and silicon area overhead. A ring interconnect is particularly well suited to achieve all of these design requirements [3]. The implementation details for accomplishing the design target will be described in this paper. Figure 9.4.1 is a floorplan view of the chip design showing the relative placement of the 10 ring stops (Cbox, Sbox), the co-located cores and cache (LLC), and the ring interconnect. The ring interconnect consists of two sets of physical channels that communicate in opposite directions, clock-wise (CW) and counterclock-wise (CCW). Each ring stop can independently handle ring traffic fr

👥 作者与机构

Cheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang,

Tejpal Singh, Jim Vash, Bo Wang, Tom Wang Intel, Hudson, MA Nehalem-EX® is the most recent product in the family of the X86