reflects the growing need for lower-power chip-to-chip interfaces for computing systems. Boardlevel transceivers using a variety of low-power circuit techniques have demonstrated power efficiencies as low as 2.2mW/(Gb/s) across four data lanes [1]. Because power efficiency generally degrades as the per-lane data rate increases
Frank O’Mahony, Joseph Kennedy, James E. Jaussi,
Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper Intel, Hillsboro, OR The recent emphasis on power efficiency in serial I/O [1-4]