In Situ Delay-Slack Monitor for High-Performance Processors Using An All-Digital Self-Calibrating 5ps Resolution Time-to-Digital Converter

📋 论文概要

该论文提出了一种用于高性能处理器的原位延迟松弛监测器，采用全数字自校准的5ps分辨率时间数字转换器，直接测量路径时序裕量以应对工艺、电压和温度变化。相比传统增加裕量的方法或复杂的纠错方案，该设计以最小侵入性实现了高精度监测，有助于动态调整时序、提升性能并降低功耗。

💡 主要创新点

• 提出全数字自校准的5ps分辨率时间数字转换器，实现原位延迟松弛监测，避免传统模拟电路的复杂性。
• 采用最小侵入式设计，直接嵌入关键路径中，能够捕获局部PVT变化，无需额外时序裕量或复杂纠错逻辑。

🏷 关键词

📄 原文摘要

susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses relies on canary circuits [1] or sensors [2], which are simple to implement but cannot account for local variations. A more recent approach, called Razor, uses delay speculation coupled with error detection and correction to remove all margins but also imposes significant design complexity [3]. In this paper, we present a minimally-invasive in situ delay slack monitor that directly measures the timing margins on critical timing signals, allowing margins due to both global and local PVT variations to be removed. At the heart of the monitor is an all-digital, self-calibrating time-to-digital converter (TDC) consisting of a 30-bit Vernier chain (

👥 作者与机构

David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik,

Jae-sun Seo, Dennis Sylvester, David Blaauw University of Michigan, Ann Arbor, MI Advanced CMOS technologies have become highly