A 45nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O

📋 论文概要

该论文提出了一种45nm SOI-CMOS工艺下的双PLL处理器时钟系统，用于支持PCI Express、DisplayPort和TMDS等多协议I/O接口。通过环振VCO PLL实现了0.99ps rms抖动，并可进一步降低至0.55ps，有效降低了多协议时钟系统的成本和功耗。

💡 主要创新点

• 采用双PLL架构，分别针对不同协议需求优化时钟生成，提高灵活性。
• 环振VCO PLL在45nm SOI-CMOS工艺下实现了亚皮秒级抖动性能，并通过电路技术进一步降低抖动。
• 集成了多协议支持，减少了独立时钟源的数量，降低了系统成本和功耗。

🏷 关键词

📄 原文摘要

Oshima1, Bruce Andrew Doyle1, Roland Bakalski2, Richard Joseph DeSantis1, Anand Thiruvengadam1, Charles Lin Wang1, Gerry Robert Talbot1, Emerson S Fang1 1 AMD, Sunnyvale, CA Global Foundries, Dresden, Germany 2 As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express®, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in Fig. 13.2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to

👥 作者与机构

Dennis Michael Fischette1, Alvin Leng Sun Loke1, Michael Masanori