New multi-gate transistor structures such as the FinFET and Trigate FET provide opportunities to reduce channel lengths that are controlled largely by the thin body of the fin instead of by channel doping [8,9]. Reduced susceptibility to random channel-doping fluctuations, improved drain-induced-barrier lowering, smaller sub-threshold swing, and improved channel carrier mobility due to smaller vertical electric fields, are advantages offered by the FinFET and

📋 论文概要

本文综述了FinFET和Tri-gate FET等多栅极晶体管结构在继续缩小晶体管沟道长度方面的机会，并参考了ITRS 2009版对微处理器印刷栅极长度持续缩小的预测。论文旨在探讨新材料和器件结构创新如何克服传统MOSFET缩放限制，推动半导体技术继续沿着摩尔定律发展。

💡 主要创新点

• 提出多栅极结构（如FinFET和Tri-gate FET）可有效抑制短沟道效应，实现更小的栅极长度。
• 结合新材料和器件结构创新，为继续缩小晶体管和互连特征尺寸提供了新途径。

🏷 关键词

📄 原文摘要

The materials and device-structure innovations discussed in the three preceding paragraphs, although not explicitly considered in the original scaling theory of MOSFETs, provide significant opportunities to continue to scale down the minimum feature sizes of transistors and interconnects. These opportunities are myriad and are taken into account in some detail by numerous experts in preparing various editions of the International Technology Roadmap for Semiconductors (ITRS) [14]. The 2009 ITRS projects microprocessor printed-gate length to continue rapid scaling from approximately 50nm in 2009 to less than 10nm in 2024; and that the number of transistors per chip (N) for high-performance microprocessors at production will continue to scale rapidly from 2.2 billion in 2009 to 70.8 billion in 2024. This continued rapid scaling of both F and N will depend critically on new discoveries and inventions that

👥 作者与机构

Trigate FET structures. However, increased transistor-parameter variability or, tolerances are an issue of growing importance [12,13].