⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了一款采用32nm工艺的32Gb MLC NAND闪存芯片，面积仅为159mm²，并实现了200MB/s的异步DDR接口。通过引入DDR接口和工艺缩放，满足了高速数据传输和大存储容量的需求。
Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung Samsung Electronics, Hwasung, Korea Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in n
Hyunggon Kim, Jung-hoon Park, Ki-Tae Park, Pansuk Kwak, Ohsuk