A 16b 250MS/s IF-Sampling Pipelined A/D Converter with Background Calibration

📋 论文概要

该论文提出了一款16位250MS/s的IF采样流水线模数转换器，通过背景校准技术校正残差放大器增益误差，解决了高分辨率、高采样率ADC在无线通信应用中IF采样时的性能问题。芯片集成了输入缓冲器，实现了良好的交流性能。

💡 主要创新点

• 采用背景校准技术实时校正残差放大器增益误差，无需中断正常转换过程。
• 实现了16位分辨率下250MS/s的高采样率，并支持IF采样，适用于无线通信系统。

🏷 关键词

📄 原文摘要

Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed Analog Devices, Greensboro, NC Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the system design. We describe a 16b ADC with a sample rate up to 250MS/s that employs background calibration of the residue amplifier (RA) gain errors. The ADC has an integrated input buffer and is fabricated on a 0.18µm BiCMOS process. When the input buffer is bypassed, the SNR is 77.5dB and the SFDR is 90dB at 10MHz input frequency. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The ADC consumes 850mW from a 1.8V supply, and the input buffer consumes 150mW from a 3V supply. The input span is 2.6Vp-p and

👥 作者与机构

Ahmed M.A. Ali, Andy Morgan, Chris Dillon, Greg Patterson,