A 222mW H.264 Full-HD Decoding Application Processor with x512b Stacked DRAM in 40nm

📋 论文概要

该论文提出了一种混合架构的应用处理器，结合软件方案与多核处理器，用于H.264全高清解码，解决了传统硬件引擎无法灵活处理新应用的问题。芯片采用40nm工艺，功耗仅222mW，并集成了512b堆叠DRAM。

💡 主要创新点

• 提出软件与多核处理器结合的混合架构，兼顾灵活性与高性能。
• 集成512b堆叠DRAM，大幅提升内存带宽并降低功耗。
• 在40nm工艺下实现222mW超低功耗的全高清H.264解码。

🏷 关键词

📄 原文摘要

Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki Toshiba, Kawasaki, Japan Today’s multimedia mobile devices must support a wide range of multimedia applications in addition to full high-definition (Full-HD) video processing. Conventional hardware engine approaches [1-3] cannot handle new applications that may be required once the chips are fabricated. We report an application processor with a hybrid architecture that combines a software solution with a multi-core processor [4] for various applications and a hardware solution with hardware engines for low-power and specific high-performance tasks such as Full-HD video and 3D graphics. Another issue faced in multimedia mobile devices is to achieve high memory bandwidth with low power consumption. DDR memory connections in System-in-Package (SiP) technologies need a

👥 作者与机构

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida,