A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction

📋 论文概要

该论文提出了一款7Gb/s/pin的GDDR5 SDRAM，实现了2.5ns的bank-to-bank激活时间，并且消除了bank-group限制，从而提升了3D图形系统的内存性能。

💡 主要创新点

• 实现了7Gb/s/pin的高速数据速率，满足高分辨率图形需求。

📄 原文摘要

Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun Samsung Electronics, Gyeonggi, Korea In the development of 3D graphic systems for higher resolution and more realistic modeling and rendering, graphic memories also have been playing a critical role to offer the required high bandwidth. Currently, GDDR5 SDRAM’s provide with 7Gbps per pin speed [1], reaching their physical limit originated from single-ended signaling nature: noise in reference voltage and power, and channel crosstalk. Especially, the channel crosstalk takes a dominating portion in 7Gbps timing budget, becoming the main barrier for further speed improvement. Although there has been researc

👥 作者与机构

Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park,