A 4.5mW/Gb/s 6.4Gb/s 22+1-Lane SourceSynchronous Link RX Core with Optional Cleanup PLL in 65nm CMOS

📋 论文概要

本文提出一种低功耗紧凑型差分源同步接收器PHY，包含22个数据通道和1个时钟通道，支持多种高速串行链路标准（4.8-6.4Gb/s），通过可选的清洗PLL降低抖动，解决了多通道源同步接收中的功耗和性能问题。

💡 主要创新点

• 采用源同步架构，利用相关抖动跟踪特性降低对时钟抖动的严格要求
• 集成22+1通道的低功耗接收器核心，能效达4.5mW/Gb/s
• 可选的清洗PLL用于进一步降低时钟抖动，支持多标准兼容

🏷 关键词

📄 原文摘要

Rüeschlikon, Switzerland 2 Source synchronous links are often used in server systems for multi-lane highspeed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links. Unique to this design is how a quadrature clock is derived from the received clock, using either a polyphase filter (PPF) or a cleanup PLL, allowing a direct

👥 作者与机构

Robert Reutemann1, Michael Ruegg1, Fran Keyser2, John Bergkvist2,

Daniel Dreps3, Thomas Toifl4, Martin Schmatz4 1 Miromico, Zürich, Switzerland IBM STG, Burlington, VT 3 IBM STG, Austin, TX 4 IBM Zurich Research Laboratory,