An x86-64 Core Implemented in 32nm SOI CMOS

📋 论文概要

本文实现了一个基于32nm SOI CMOS工艺的x86-64核心，面积9.69mm²，集成超3500万晶体管（不含L2缓存），工作频率超过3GHz。该核心通过设计和电源改进，实现了2.5-25W的宽功耗范围和近零功耗门控状态，适用于移动和桌面产品。

💡 主要创新点

• 针对32nm HKMG工艺中PMOS驱动强度相对NMOS显著增加的问题，重新设计了动态电路中的keeper电路以维持正确逻辑。
• 通过多种低功耗技术和宽范围电压调节，实现了从2.5W到25W的功耗缩放以及接近零功耗的休眠状态。

🏷 关键词

📄 原文摘要

occupies 9.69mm2, contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products. The conversion to the 32nm high-κ metal-gate (HKMG) process presents several challenges not encountered in previous generations. The PMOS drive strength increased significantly relative to NMOS. This forced revision of the keeper design for dynamic nodes and caused unacceptable delay increase in some cases. To solve this, a delayed onset keeper is designed to prevent the pull-down from fighting the keeper PMOS during evaluation. Figure 5.6.1 shows an implementation of this keeper. The

👥 作者与机构

Ravi Jotwani1, Sriram Sundaram1, Stephen Kosonocky2, Alex Schaefer1,

Victor Andrade1, Greg Constant1, Amy Novak1, Samuel Naffziger2 1 AMD, Austin, TX AMD, Fort Collins, CO 2 The 32nm implementation of an AMD x86-64 core [1,2,5],