A 45nm SOI Embedded DRAM Macro for POWER7TM 32MB On-Chip L3 Cache

📋 论文概要

该论文介绍了在45nm SOI工艺上为POWER7处理器设计的32MB片上L3缓存嵌入式DRAM宏单元，解决了高性能逻辑兼容嵌入式DRAM在微处理器缓存中的应用问题。

💡 主要创新点

• 在45nm SOI工艺上实现了高密度嵌入式DRAM宏单元，用于32MB片上L3缓存。
• 通过逻辑兼容的嵌入式DRAM设计，提升了微处理器缓存的性能与密度。

🏷 关键词

📄 原文摘要

Gregory Fredeman2, Michael Sperling2, Abraham Mathews3, William Reohr4, Kavita Nair2, Nianzheng Cao2 1 IBM, Essex Junction, VT IBM, Poughkeepsie, NY 3 IBM, Austin, TX 4 IBM T. J. Watson, Yorktown Heights, NY 2 Logic-based embedded DRAM has matured into a wide range of ASIC applications, SRAM replacements [1] and off-chip caches for microprocessors [2]. While embedded DRAM has been leveraged in supercomputers such as IBM’s BlueGene/L [3], it’s use has been limited to moderate performance bulk logic technologies. Although prototypes have been demonstrated [4], DRAM has yet to be embedded on a high performance microprocessor. This paper discloses an SOI DRAM macro implemented on-chip with the IBM POWER7TM high performance microprocessor [5], and introduces enhancements to the micro sense amp (µSA) architecture [6]. This high performance DRAM macro is used to construct a large 32MB L3 cache on-chip, eliminating delay, area and power from

👥 作者与机构

John Barth1, Don Plass2, Erik Nelson1, Charlie Hwang2,