A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS

📋 论文概要

该论文提出了一种在90nm CMOS工艺下实现的16Gb/s高速有线收发器，采用首抽头前馈均衡（FFE）和三抽头决策反馈均衡（DFE）架构，旨在消除高速芯片间通信中的码间干扰（ISI）。通过解决环路展开方法在16Gb/s信号均衡中面临的额外组件问题，实现了高速多抽头DFE的设计。

💡 主要创新点

• 提出了一种结合首抽头FFE和三抽头DFE的均衡架构，有效提升了高速信号处理能力。
• 针对环路展开方法在16Gb/s应用中引入的额外组件问题进行了优化，降低了电路复杂度。

🏷 关键词

📄 原文摘要

Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing intersymbol interference (ISI) in high-speed chip-to-chip communication. A loopunrolled approach is widely used in work toward the design of high-speed multitap DFEs. It eliminates the feedback operation in first post-cursor equalization [1-3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2nd-tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed

👥 作者与机构

Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno

NEC, Sagamihara, Japan