A Calibration-Free 800MHz Fractional-N Digital PLL with Embedded TDC

📋 论文概要

提出一种无校准的分数-N数字PLL，通过将时间数字转换器（TDC）嵌入VCO内部并采用失配滤波技术改善线性度，仅使用整数-N分频器即可实现分数-N功能，无需额外的校准电路。

💡 主要创新点

• 将TDC嵌入VCO内部，简化了传统DPLL中TDC与VCO的接口，降低了对TDC线性度的要求。
• 提出失配滤波技术，有效改善TDC的线性度，从而消除分数-N DPLL所需的校准步骤。
• 仅使用整数-N分频器实现分数-N频率综合，避免了复杂的分数分频器设计和杂散问题。

🏷 关键词

📄 原文摘要

Atheros Communications, Santa Clara, CA Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conventional analog charge-pump based PLLs [1-4]. This paper presents a calibration-free fractional-N DPLL that uses only an integer-N divider with a time-to-digital converter (TDC) embedded inside the VCO and utilizes a mismatch filtering technique to improve the linearity of the TDC. One distinctive difference in a DPLL architecture compared to an analog PLL lies in its digital signal processing capabilities. In an analog PLL, injecting an auxiliary DC current into a charge pump can create a static phase offset between the reference and feedback clocks; therefore, an arbitrary offset (or fractional-N) frequency can be created by integrating a variable auxiliary DC current [5]. While

👥 作者与机构

Mike Shuo-Wei Chen, David Su, Srenik Mehta