High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS

📋 论文概要

该论文提出了一种采用自适应预加重技术的片上信令方案，旨在解决高性能VLSI系统中互连线的延迟、带宽和能量挑战。通过减少中继器数量并优化信令效率，实现了高带宽和低能耗的片上通信。

💡 主要创新点

• 提出自适应预加重电路，动态调整驱动强度以补偿信道损耗，提升信号完整性
• 结合电容模式或电流模式信令，降低能量消耗并减少中继器使用
• 在90nm CMOS工艺中验证了高带宽和低能耗的片上互连性能

🏷 关键词

📄 原文摘要

wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter

👥 作者与机构

Jae-sun Seo1, Ron Ho2, Jon Lexau2, Michael Dayringer2,

Dennis Sylvester1, David Blaauw1 1 University of Michigan, Ann Arbor, MI, Sun Microsystems, Menlo Park, CA 2 Long on-chip