A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance

📋 论文概要

本文提出了一种采用45nm工艺的弹性和自适应微处理器核心，通过集成时序错误检测和恢复电路，有效应对电压跌落、温度变化和器件老化等动态变化，从而消除传统设计中不必要的频率或电压保护带，显著提升性能和能效。

💡 主要创新点

• 提出了一种基于时序错误检测的自适应机制，允许处理器在接近临界条件下运行，同时通过快速恢复确保正确性。
• 实现了动态电压和频率调整技术，根据实时工作负载和环境变化自动优化功耗与性能。

🏷 关键词

📄 原文摘要

Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De Intel, Hillsboro, OR Microprocessors experience a wide range of dynamic variations, including voltage droops, temperature changes, and device aging, which vary across applications and systems. The necessity of ensuring correct operation even under infrequent worst-case conditions results in clock frequency (FCLK) or supply voltage (VCC) guardbands that degrade performance and increase energy consumption. In this paper, a research microprocessor core is described with resilient and adaptive circuits to mitigate dynamic variation guardbands for maximizing throughput or minimizing energy. The resiliency features consist of embedded error-detection sequentials (EDS) [1-4] and tunable replica circuits (TRC) [5] in conjunction with error-recovery circuits to detect and correct timing errors. A

👥 作者与机构

James Tschanz, Keith Bowman, Shih-Lien Lu, Paolo Aseron,