A 32nm High-κ Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

📋 论文概要

该论文提出了一种采用32nm高k金属栅极工艺的SRAM，通过自适应动态稳定性增强技术，解决了工艺缩放导致的位单元设计余量缩小问题，实现了低电压操作下的性能与功耗平衡。

💡 主要创新点

• 提出自适应动态稳定性增强电路，根据工艺变化动态调整辅助偏置，改善读写余量。
• 在32nm高k金属栅极工艺中实现低电压SRAM操作，满足严格的功耗约束。

🏷 关键词

📄 原文摘要

performance, and density requirements as Moore’s law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no longer able to fully realize the benefits of scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. VCC scaling is especially important to meet increasingly stringent power constraints [1]. Circuit techniques proposed in recent years enable SRAM VCC scaling by expanding read and write margins [2-6]. However, the improved design margins for SRAM VCC scaling are often achieved with significant design overhead, e.g., additional power supply [4], increased circuit complexity [5], and

👥 作者与机构

Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl,

Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang Intel, Hillsboro, OR SRAM scaling faces increasing challenges in meeting power,