A 3MHz-BW 3.6GHz Digital Fractional-N PLL with

📋 论文概要

该论文提出了一种3MHz带宽、3.6GHz的数字分数N锁相环，结合了4ps时间数字转换器（TDC）与数字线性化算法，以及带有失配消除算法的反馈相位插值器。解决了TDC非线性导致的杂散问题以及相位插值器失配引起的相位误差，实现了快速准确的杂散消除。

💡 主要创新点

• 采用4ps分辨率的亚门延迟TDC，并结合数字线性化算法实现无乘法器计算，快速消除杂散。
• 提出反馈相位插值器与数字失配消除算法，无需复杂校准环路即可后消除相位误差。

🏷 关键词

📄 原文摘要

spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digital linearization algorithm and a feedback phase interpolator with mismatch cancellation algorithm. In contrast to other TDC linearization approaches [3], this structure allows multiplier-free computations, fast and accurate spur cancellation, as well as digital post-cancellation of phase errors induced by the phase interpolator mismatches, avoiding more complex calibration loops [4]. Figure 26.5.1 shows the schematic of the PLL. Plain implementations of digital fractional-N PLLs normally require 9 to 10b TDCs. The resolution needs to be as

👥 作者与机构

Sub-Gate-Delay TDC, Phase-Interpolation Divider, and Digital Mismatch Cancellation

Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea Lacaita Politecnico di Milano, Milano, Italy Digital Fractional-N PLLs allows easy cancellation of ΔΣ quantization noise and