⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文实现了一款面向3GPP-LTE标准的Turbo解码器ASIC，在0.13µm CMOS工艺下达到了390Mb/s的吞吐量，芯片面积仅为3.57mm²。该设计针对低成本低功耗的LTE用户设备，解决了高数据率下turbo解码的挑战。
devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years, development of cost-effective and low-power LTE user equipment is currently keeping the wireless industry preoccupied. While the 1st-generation terminals will target 100Mb/s in the downlink, the MIMO-based LTE standard is capable of 326.4Mb/s [1] operation, which is more than 20× that of HSDPA. As with HSDPA, turbo decoding will be among the challenges (along with MIMO detection) in computation intensity, now threatening to be 20× higher. This contribution explores the feasibility of achieving the LTE maximum throughput with a
Christoph Studer1, Christian Benkeser1,2, Sandro Belfanti1,
Quiting Huang1,2 1 ETH Zürich, Zürich, Switzerland Advanced Circuit Pursuit, Zollikon, Switzerland 2 Recent popularity of smart phones, netbooks, and other mobile broadband