⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种在32nm CMOS工艺下实现的32Gb MLC NAND闪存，通过Vth耐久性增强方案（包括浮栅耦合取消和PV状态读取）来减少ISPP步长，从而改善编程性能。测量结果显示编程时间改善了25.4%。
Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, InSuk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jaekwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi, Taeho Jeon, Joong-Seob Yang, YoHwan Koh From (1) and (2), ΔISPP can be reduced with proposed FG coupling cancellation PV state read in the amount of Vshift. As ΔISPP at MSB even page increases, program performance improvement can be gained. Figure 24.8.3 shows the measurement results of program time comparison. By applying proposed FG coupling cancellation PV state read, 25.4% time reduction was achieved at MSB even page program. Hynix Semiconductor, Icheon, Korea Another challenging phenomenon that is hard to overcome as technology shrinks is retention Vth shift. The fact that optimum read levels differ with amount of retention shift makes it difficult for fixed read levels to guarantee all cases. Moving
Changhyuk Lee, Sok-Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun