A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC Achieving Over 90dB SFDR

📋 论文概要

该论文提出了一种12位22.5/45MS/s的SAR ADC，在0.059mm²的小面积和3.0mW的低功耗下实现了超过90dB的SFDR。通过优化开关逻辑和电容阵列，解决了高速高精度SAR ADC中功耗与面积之间的矛盾。

💡 主要创新点

• 采用分段电容阵列和高效开关逻辑，在保持高线性度的同时显著降低功耗和面积。
• 通过动态比较器和数字校准技术，实现了超过90dB的SFDR，适用于高速高精度应用。

🏷 关键词

📄 原文摘要

CMOS technology scaling has opened a pathway to high-performance analogto-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the conversion architectures that rely on the high switching speed of process technology, and is thus distinctively known for its superior energy efficiency, small chip area, and good digital compatibility. When properly implemented, a SAR ADC also benefits from a potential rail-to-rail input swing, 100% capacitance utilization during input sampling (thus low kT/C noise), and insensitivity to comparator offsets during the conversion process. The linearity-limiting factors for SAR ADC are capacitor mismatch, sampling switch non-idealities, as well as the reference voltage settling issue due to the high internal switching speed of the DAC. In this work, a sub-radix-2 SAR ADC is presented, which employs a perturbation-based

👥 作者与机构

Wenbo Liu, Pingli Huang, Yun Chiu

University of Illinois at Urbana-Champaign, Urbana, IL