⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了一款采用45nm CMOS工艺制造的48核IA-32消息传递处理器，支持动态电压频率调整(DVFS)。解决了众核处理器高效通信和功耗管理的问题。
David Finan1, Gregory Ruhl1, David Jenkins1, Howard Wilson1, Nitin Borkar1, Gerhard Schrom1, Fabrice Pailet1, Shailendra Jain2, Tiju Jacob2, Satish Yada2, Sraven Marella2, Praveen Salihundam2, Vasantha Erraguntla2, Michael Konow3, Michael Riepen3, Guido Droege3, Joerg Lindemann3, Matthias Gries3, Thomas Apel3, Kersten Henriss3, Tor Lund-Larsen3, Sebastian Steibl3, Shekhar Borkar1, Vivek De1, Rob Van Der Wijngaart4, Timothy Mattson5 1 Intel, Hillsboro, OR Intel, Bangalore, India 3 Intel, Braunschweig, Germany 4 Intel, Santa Clara, CA 5 Intel, DuPont, WA 2 Current developments in microprocessor design favor increased core counts over frequency scaling to improve processor performance and energy efficiency. Coupling this architectural trend with a message-passing protocol helps realize a data-center-on-a-die. The prototype chip (Figs. 5.7.1 and 5.7.7) described in this paper integrates 48 Pentium™ class IA-32 cores [1] on a 6×4 2D-mesh
Jason Howard1, Saurabh Dighe1, Yatin Hoskote1, Sriram Vangal1,