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本文提出了一种在40nm CMOS工艺下实现的鲁棒数字DC-DC转换器，能够提供轨到轨输出范围。针对先进工艺中低电压下传统模拟架构不适用的问题，采用数字控制环路并降低了对模数转换器的要求，实现了具有竞争力的性能。
TSMC, Austin, TX The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1-3]. The DC-DC converter presented here uses a robust digital control loop with minimal demands on the ADC. Still, competitive performance is achieved. The chip can operate in pulse-width modulation (PWM) and pulse-frequency modulation (PFM) mode. The PWM mode is discussed here. Figure 10.2.1 shows a traditional “buck” converter and the alternative digital approach used here. The analog error amplifier has been replaced by an ADC followed by a digital filter. The ADC mimics the differencing and gain operation of
Eric G Soenen, Alan Roth, Justin Shi, Martin Kinyua, Justin Gaither, Elizabeth Ortynska