A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18µm CMOS

📋 论文概要

该论文提出了一种1GHz的全数字锁相环(ADPLL)，采用子指数时间数字转换器(TDC)实现了1.25ps的最小分辨率。该TDC通过新颖的架构解决了传统Vernier延迟链在分辨率、检测范围和功耗之间的矛盾，实现了高分辨率和大检测范围。

💡 主要创新点

• 提出了子指数(Sub-Exponent) TDC架构，突破了传统TDC分辨率受限于单级反相器延迟的限制。
• 实现了1.25ps的高时间分辨率，同时保持了较大的检测范围，并降低了功耗和转换时间。

🏷 关键词

📄 原文摘要

since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Wellestablished data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input

👥 作者与机构

Seon-Kyoo Lee, Young-Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

Pohang University of Science and Technology, Pohang, Korea The resolution of multi-bit linear TDC is closely related to process technology