A Wafer-Level Heterogeneous Technology Integration for Flexible Pseudo-SoC

📋 论文概要

本文提出一种晶圆级异构技术集成方法，用于实现灵活的伪系统级芯片（Pseudo-SoC），解决了MEMS与标准CMOS工艺不兼容时难以实现高密度集成的问题。该方法通过晶圆级工艺整合不同技术，达到与单片集成SoC相当的集成密度。

💡 主要创新点

• 提出晶圆级异构集成方法，实现MEMS与CMOS LSI的兼容集成
• 引入伪SoC（Pseudo-SoC）架构，在工艺不兼容时仍能实现高密度系统集成
• 利用晶圆级工艺替代传统SiP中介层，提升集成密度

🏷 关键词

📄 原文摘要

implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and standard CMOS processes are incompatible. Furthermore, many MEMS-LSI integration technologies applying System in Package (SiP) technology with the interposer substrate to realize electronics devices have been reported. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced MEMS-LSI integration technology to realizing highly integrated SoC incorporating MEMS devices is required [2]. In the authors’ previous work, the pseudo-SoC realized by a wafer-level hyper

👥 作者与机构

Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki

Toshiba, Kawasaki, Japan The MEMS-LSI integration technologies that have been reported are mainly