⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种采用双边缘注入锁定振荡器的突发模式时钟数据恢复电路，实现了1.296至5.184 Gb/s的数据速率和2.4 mW/(Gb/s)的功耗效率，解决了移动消费电子中高速低功耗I/O链路的需求。
Yasunori Tsukuda1, Yuki Yagishita1, Hironobu Konishi2, Toshiyuki Ogata2, Hisashi Owa1, Taichi Niki1, Kenji Konda1, Masahiro Sato1, Hiroshi Shiroshita1, Takeshi Ogura1, Takayuki Aoki1, Hiroki Kihara1, Sachiya Tanaka1 1 Sony, Tokyo, Japan Sony LSI Design, Yokohama, Japan 2 Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lockin time should be within the period of several tens of bits. Therefore, the PLLbased phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (<20 bits), continuous-rate capability (1.296 to
Kenichi Maruko1, Tatsuya Sugioka1, Hiroaki Hayashi1, Zhiwei Zhou1,