A Mostly Digital Variable-Rate Continuous-Time ADC ΔΣ Modulator

📋 论文概要

提出了一种主要由数字电路构成的连续时间ΔΣ调制器，消除了传统模拟积分器、反馈DAC等组件，且不需要低抖动时钟。在65nm LP CMOS工艺中实现了与先前ΔΣ调制器相当的性能，但面积显著减小。

💡 主要创新点

• 提出了一种大部分由数字电路构成的连续时间ΔΣ调制器架构，避免使用模拟积分器、反馈DAC、比较器和参考电压。
• 性能主要取决于数字电路速度，无需低抖动时钟，特别适用于高速数字工艺。
• 在65nm LP CMOS工艺中实现了小面积、低功耗的原型，性能与先进ΔΣ调制器相当。

🏷 关键词

📄 原文摘要

modulator is presented that consists mostly of digital circuitry. It does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a lowjitter clock. Unlike conventional ΔΣ modulators, its performance depends mainly on the speed of its digital circuitry, so it works best in IC processes optimized for fast digital circuitry. A 65nm LP CMOS prototype is presented with comparable performance to and much lower area than previously published ΔΣ modulators. As shown in [1], a voltage-controlled ring oscillator (VCRO) with its inverters sampled at the desired output sample-rate followed by a phase decoder and digital differentiator is equivalent to a 1st-order ΔΣ modulator. However, VCRO nonlinearity and the high spurious tone content of 1st-order ΔΣ quantization noise

👥 作者与机构

Gerry Taylor1,2, Ian Galton1, 1

University of California, San Diego, CA Analog Devices, San Diego, CA 2 A digitally background calibrated ring oscillator ADC ΔΣ