A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS

📋 论文概要

本文提出了一种无时间数字转换器（TDC）的分数-N数字锁相环（PLL），采用数字控制环形振荡器，在65nm CMOS工艺中实现了1.4ps均方根周期抖动。该设计避免了传统TDC架构的复杂性和校准需求，同时支持分数-N合成，适用于扩频时钟等应用。

💡 主要创新点

• 提出无TDC的分数-N数字PLL架构，通过数字控制环形振荡器实现低抖动，降低了系统复杂度和校准开销。
• 采用数字控制环形振荡器替代传统压控振荡器，结合数字相位检测实现分数-N合成，无需TDC即可达到1.4psrms周期抖动性能。

🏷 关键词

📄 原文摘要

State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1-3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4-6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate. This paper introduces a digital PLL architecture, which, in order to reduce the phase quantization error without a traditional TDC, exploits the multiphase output of a 3-phases digitally controlled ring oscillator (DCRO) providing built-in

👥 作者与机构

Werner Grollitsch, Roberto Nonis, Nicola Da Dalt

Infineon Technologies, Villach, Austria