A 10b 100MS/s 4.5mW Pipelined ADC with a Time Sharing Technique

📋 论文概要

该论文提出了一种采用时间共享技术的10位100MS/s流水线ADC，仅消耗4.5mW功耗。通过时间共享MDAC中的运算放大器，有效减少了芯片面积和静态功耗，在保持中等速度和高分辨率的同时实现了低功耗设计。

💡 主要创新点

• 提出时间共享技术，使多个流水线级共享同一个运算放大器，大幅降低功耗。
• 优化了MDAC的时序和电容匹配，确保在共享运放条件下仍能维持10位线性度。

🏷 关键词

📄 原文摘要

For the applications requiring medium-to-high resolution ADCs, the pipelined architecture is considered to be the most optimal structure in terms of power consumption and area. With range overlap and redundant bit at each pipelined stage, the sub-ADC can tolerate large comparator offsets, thereby, leaving the linearity and accuracy requirements for the DAC and the residue gain stage. Typically, the multiplying DAC (MDAC), which is the combination of a DAC and a gain stage, requires a high-gain wide-bandwidth opamp and is the most critical building block. The opamps draw static currents from their power supplies and consume most of the power in a pipelined ADC. Many techniques have been reported to achieve a low-power design by avoiding the high-gain opamp, such as zero-crossing based circuits [1, 2], dynamic source-follower amplification

👥 作者与机构

Yen-Chuan Huang, Tai-Cheng Lee

National Taiwan University, Taipei, Taiwan