A 2.1-to-2.8GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC

📋 论文概要

该论文提出了一种2.1至2.8GHz的全数字频率合成器，采用时间窗口TDC技术，在实现低相位噪声的同时降低了功耗，解决了WiFi/WiMAX等无线系统中高分辨率TDC功耗大的问题。

💡 主要创新点

• 提出时间窗口TDC，通过仅在相位误差窗口内工作来降低功耗，同时保持高时间分辨率。
• 采用全数字架构，消除了大尺寸片上无源滤波器，并改善了低电源电压下的性能。

🏷 关键词

📄 原文摘要

NEC, Kawasaki, Japan NEC Electronics, Kawasaki, Japan 2 All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages. Figure 26.2.1 shows a block diagram of the ADPLL. The integer part of a digitally controlled oscillator (DCO) outp

👥 作者与机构

Takashi Tokairin1, Mitsuji Okada2, Masaki Kitsunezuka1, Tadashi Maeda1, Muneo Fukaishi1